1. Field of the Invention
This invention relates generally to MOS logic networks which use multi-phase clock circuits in ratioed and ratioless configurations.
2. Description of the Prior Art
MOS logic networks are basically of two types, static logic networks and dynamic logic networks. MOS static networks are similar to the type of logic networks employed in bipolar integrated circuits in that they do not rely upon inherent capacitances for the storage of charges. Rather, they include gates which are either conductive or nonconductive depending on the particular logic state.
The timing of MOS static logic networks is typically accomplished by shifting data with series coupling devices and dc flip-flops. Although such static logic circuits provide generally good noise immunity and rapid conversion to MOS-LSI with minimum redesign, they suffer from extremely high power requirements. Also, they generally require a larger number of devices per logic function and permit fewer logic functions per array.
Dynamic logic networks use multiphase clock signals in both ratioed and ratioless configurations. A fundamental characteristic of a dynamic logic network is that it uses load devices which are clocked on and off synchronously as a function of system or subsystem timing. Inherent capacitance is used for the temporary storage of charge to retain information in the logic networks. Dynamic logic networks consume less power and require less chip area per logic function than do the static logic networks. In addition, the delay function can be mechanized with few devices and system timing problems can also be simplified.
Two schemes of dynamic logic dominate in custom circuit design. These schemes are a two-phase ratioed logic scheme and a four-phase ratioless logic scheme. The number of phases in a particular scheme connotes the number of logic levels which can be implemented in a single bit time.
In ratioed logic schemes generally, when both the load and input devices are conducting, there is a dc current path from the power or clock supply to ground. This provides the high power dissipation properties which are characteristic of these rotioed circuits. Also, larger device geometries are needed to implement a given logic function than with the ratioless schemes. Furthermore, the number of series logic gates which can be reasonably accommodated is restricted by an impedance ratio requirement wherein the impedance of the load device is preferably at least 20 times the total impedance of all the series input devices. Although the two-phase rotioed logic networks are slower, they are generally preferred since they provide for simple noise analysis. Also, they are much less complex than typical four-phase networks since they use two clocks instead of four clocks.
If noise can be analyzed properly, it is generally felt that the four-phase ratioless logic scheme provides a better logic network than does the two-phase ratioed logic scheme. Since there are no ratio requirements to be met, the circuits can be formed from generally smaller unit sized transistors. Also, power consumption is significantly reduced in spite of the fact that the four clocks in the four-phase ratioless scheme draw more dynamic current than the two clocks in the two-phase ratioed scheme. However, in the four-phase ratioless logic network, noise can be critical and noise analysis can be quite difficult.
The four-phase schemes typically include logic gate types which are connected in series or parallel to form logic cells or networks. Each of the gate types in the series typically drives one or more of the other gate types in the same cell or even another cell. The use of ratioless gate types in such a network has caused several problems that are of particular interest to the present invention.
One such problem will be referred to herein as a capacitance sharing problem. In some four-phase ratioless logic networks and all two-phase ratioless logic networks, there is a sharing of capacitance charge between the output node and the internal node during the evaluation mode.
If the inherent capacitances associated with the output and internal nodes are substantially equal, the charge on the output node will be reduced to approximately one-half the charge initially provided by a particular gate type. Since the logic value of the gate is dependent upon the charge on the output node, any noise associated with a subsequent gate may further reduce the charge on the output node and result in an erroneous evaluation of the logic state of the gate.
Another problem associated with the ratioless logic schemes is commonly referred to as a negative noise problem. If a particular gate type in the cell or network is driven by the preceding gate type and the precharge on the particular gate type is high or true, a large amount of inherent capacitance coupling will pull the output of the preceding gate type negative as the output of the particular gate type logically changes to low or false.
Another more serious problem associated with most 4-stage ratioless schemes is positive noise. If a particular gate is driven by a preceding gate in the network and the particular gate is precharged low or false, a significant amount of inherent capacitance coupling will pull the output of the preceding gate positive as the output of the particular gate is charged positive or true. Since most MOS FET processes provide less of a safety margin against positive noise than against negative noise, this can be a particularly serious problem.